A Bit-Serial Architecture for a Multiplierless DCT

Authors

  • S. Choomchuay Department of Electronics, Faculty of Engineering, and Research Center for Communications and Information Technology (ReCCIT), King Mongkut’s Institute of Technology Ladkrabang(KMITL), Chalongkrung Road, Ladkrabang, Bangkok 10520, Thailand
  • S. Timakul Department of Electronics, Faculty of Engineering, and Research Center for Communications and Information Technology (ReCCIT), King Mongkut’s Institute of Technology Ladkrabang(KMITL), Chalongkrung Road, Ladkrabang, Bangkok 10520, Thailand

DOI:

https://doi.org/10.32890/jict2003.2.1.2

Keywords:

DCT, multiplierless DCT, binDCT, VLSI, image coding

Abstract

This paper describes the implementation of a multiplierless 1-D DCT which is also applicable to 2-D computation. The key idea is based on the binary DCT of which multipliers are replaced by lifting parameters that essentially are shifts and adds. For lower power applications and smaller hardware size, a bit-serial architecture was invoked in the implementation of such an algorithm. Varying data word length, MSE obtained from our approach and some similar algorithms are also investigated and reported.

 

References

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Published

28-05-2003

Issue

Vol. 2 No. 1 (2003): Journal of Information and Communication Technology (JICT) Vol. 2, No.1 June 2003

Section

Articles

How to Cite

Choomchuay, S., & Timakul, S. (2003). A Bit-Serial Architecture for a Multiplierless DCT. Journal of Information and Communication Technology, 2(1), 15-30. https://doi.org/10.32890/jict2003.2.1.2

Research impact

Harvested 2026-09-06
1 citations, from OpenAlex — the highest of the sources checked

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Identifiers DOI 10.32890/jict2003.2.1.2 OpenAlex W1607469587